Chip Warpage Induced by Tapered Through-Silicon Vias: A Numerical Analysis PROJECT TITLE :Chip Warpage Induced by Tapered Through-Silicon Vias: A Numerical AnalysisABSTRACT:This paper issues chip warpage caused by thermal expansion mismatch between tapered copper (Cu) through-silicon vias (TSVs) and the encompassing silicon (Si) matrix. Systematic numerical finite-element modeling is performed to simulate the periodic array of Cu TSVs. It is demonstrated that important chip curvature can develop as a result of the tapered TSV geometry. The results of taper angle, diameter, and density of TSVs; wafer thickness; and intermediate layers between Cu and Si are investigated. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest A Fuzzy Logic-Based Retrofit System for Enabling Smart Energy-Efficient Electric Cookers MoVieUp: Automatic Mobile Video Mashup