PROJECT TITLE:

RTL implementation for AMBA ASB APB protocol at system on chip level - 2015

ABSTRACT:

In today's era AMBA (advanced microcontroller bus architecture) specifications have gone so much beyond the Microcontrollers. In this project, AMBA (Advanced Microcontroller Bus Architecture) ASB APB (Advanced system bus - Advanced Peripheral Bus) is implemented. The goal of the proposed project is to synthesis, simulate advanced interface between AMBA ASB and APB. The methodology adopted for the proposed project is Verilog language with finite state machine models designed in ModelSim Version 10.three and Xilinx-ISE style suite, version 13.four is used to extract synthesis, design utilization summary and power reports. For the implementation APB Bridge, arbiter and decoder are designed. In AMBA ASB APB module, master gets into contact with APB bus. Arbiter determines master's status and priority and then, starts communicating with the bus. For selecting a bus slave, decoder uses the correct address lines and an acknowledgement is given back to the bus master by the slave. An RTL read and an extracted design summary of AMBA ASB APB module at system on chip are shown in result section of the project. Higher style complexities of SoCs architectures introduce the facility consumption into picture. The varied power elements contribute in the facility consumptions which are extracted by the ability reports. So, power reports generate a higher understanding of the facility utilization to the designers. These are clocks total power that consumes of 0.sixty six mW, hierarchy total power that consumes of one.05 mW, hierarchy total logical power which consumes of 0.thirty mW and hierarchy total signal power which consumes of 0.seventy four mW powers in the proposed style. Graph is additionally plotted for clear understanding of the breakdown of powers.


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