PROJECT TITLE :

Evaluation of testability enhancement using software prototype

ABSTRACT:

The useful delay-fault models, that are based on the input stimuli and correspondent responses at the outputs, cowl transition faults at the gate level quite well. This statement forms the idea for the analysis and comparison of different methods of design for testability (DFT) using software prototype model of the circuit and to pick out the foremost acceptable one before the structural synthesis of the circuit. Together with known DFT ways (enhanced scan, launch-on-shift scan and launch-on-capture scan), the authors introduce the tactic, that is predicated on the addition of new connections to the circuit within the non-scan testing mode. In order to assess the DFT ways, the practical take a look at is generated for the analysed circuit and the practical delay-fault coverage for this take a look at is evaluated. Each of the considered DFT methods has its own advantages and disadvantages, since they have completely different delay fault coverage, and require totally different hardware for his or her implementation. These differences depend on the function of circuit. The experimental results are provided for the ITC??ninety nine benchmark circuits. The obtained results proved the applicability of the proposed technique.


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