PROJECT TITLE :
Design and evaluation of a high throughput robust router for network-on-chip
Network-on-chip (NoC) systems are proposed to realize high-performance computing where multiple processors are integrated into one chip. As the amount of cores will increase and also the chips are scaled in the deep submicron technology, the NoC systems become subject to physical manufacture defects and running-time vulnerability, which end in faults. The faults have an effect on the performance and functionality of the NoC systems and end in Communication malfunctions. In this study, a fault tolerant router style with an adaptive routing algorithm that tolerates faults within the network links and the router components is proposed. The approach will not require the employment of virtual channels and assures deadlock freedom. Furthermore, the experimental results show that the proposed design can tolerate multiple failures and prove robustness and fault tolerance with negligible impact on the performance.
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