Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths


The design, analysis, and implementation of an correct delay circuit used to synthesize crucial paths in a microprocessor system are presented. The delay circuit includes a unique 64-step programmable calibration delay line that is highly uniform across a wide selection of offer voltages and a reconfigurable delay path with tunable delay sensitivity to voltage variations. The calibration delay line generates delay step in picosecond vary, which is but one% of the clock cycle time for the microprocessor. The reconfigurable path is capable of increasing voltage sensitivity of the delay circuit by 40p.c and emulating the steeper frequency versus voltage slope of the microprocessor in low-voltage domain. The proposed circuit is implemented inside the essential path monitor block placed on a take a look at microprocessor core fabricated using twenty two-nm silicon-on-insulator CMOS process. Measurement results from nine take a look at cores show that the circuit tracks microprocessor timing margin modification with a slip less than 1.3% of the core operating frequency over a large offer voltage vary.

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