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  3. Computer Architecture Letters
  4. Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities
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Category: Computer Architecture Letters
By MTech Projects
MTech Projects
31.Jan
Hits: 50

Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities

ABSTRACT:

As technology scales, device reliability is becoming a fundamental problem. Even though manufacture test can guarantee product quality, due to various types of wearout and failure modes, permanent faults appear in the filed is becoming an increasingly important and real problem. Such types of wear-out creates permanent faults in devices during their lifetime, but after release to the user. In this paper, we perform a formal investigation of the impact of permanent faults on security, examine empirical evidence, and demonstrate a real attack. Our results show that permanent stuck-at faults may leave security holes in microprocessors. We show that an adversary with knowledge of a fault can launch attacks which can obtain critical secrets such as a private key in 30 seconds.

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  • Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities
  • Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks
  • Improper Signaling for Symbol Error Rate Minimization in -User Interference Channel
  • Multilevel Cache Modeling for Chip-Multiprocessor Systems
  • Adaptive Cache and Concurrency Allocation on GPGPUs
  • Atomic Streaming: A Framework of On-Chip Data Supply System for Task-Parallel MPSoCs
  • A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding
  • Properties of the Energy Transport for Plane-Parallel Polychromatic Surface Gravity Waves in Waters of Arbitrary Depth
  • PHEVs Bidirectional Charging/Discharging and SoC Control for Microgrid Frequency Stabilization Using Multiple MPC
  • Time-Aware VMFlow Placement, Routing, and Migration for Power Efficiency in Data Centers
Previous article: Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor Next article: Fault-Tolerant Vertical Link Design for Effective 3D Stacking Fault-Tolerant Vertical Link Design for Effective 3D Stacking
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