Accelerating Irregular Computation in Massive Short Reads Mapping on FPGA Co-Processor PROJECT TITLE :Accelerating Irregular Computation in Massive Short Reads Mapping on FPGA Co-ProcessorABSTRACT:Because there's an enormous quantity of genomic information, next-generation sequencing (NGS) applications cause important challenges to current computing systems. In this study, we investigate both algorithmic and architectural methods to accelerate an NGS knowledge analysis algorithm—short read mapping on commodity multi-core platform and customizable field programmable gate array (FPGA) co-processor design, respectively. A workload analysis reveals that conventional memory optimization is restricted in its irregular computation of low arithmetic intensity and non-contiguous memory access pattern. To mitigate the inherent irregular computation in mapping, we tend to have developed a FPGA co-processor primarily based on Convey computer, which employs a scatter-gather memory mechanism that exploits both bit-level and word-level parallelism. The customized FPGA co-processor achieves a throughput of Gbp per day, regarding times beyond that of current mapping tools on single CPU core. Moreover, the co-processor's power potency is times over that of a standard sixty four-core multi-processor. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Designing Efficient Index-Digit Algorithms for CUDA GPU Architectures Experimental Evidence on Decision-Making in Availability Service Level Agreements
