PROJECT TITLE :

Study of Optimal Dummy Fill Modes in Chemical–Mechanical Polishing Process

ABSTRACT:

Chip surface topography once chemical–mechanical sharpening (CMP) method is greatly influenced by the layout geometric characteristics, such as line width and line house. So as to improve surface topography, dummy fills are typically inserted between interconnects. However, this will increase coupling capacitances between interconnects and deteriorates the timing and signal integrity of the chip. In this paper, one flow to accumulate optimal dummy fill modes is proposed for both better planarity and fewer capacitance increment in specific process. For instance of using this flow, we designed check patterns with different fill modes and measured their surface topography and coupling capacitances when the CMP method. Experiment results are displayed and analyzed, and fill pointers for each better planarity and less coupling capacitance are proposed based on the results. A possible optimal fill mode is also acquired based mostly on the rules. In our flow, solely one check run is required in every process, and then all the products run in this process can use these optimal fill modes.