Development of a 3-D Process Technology for Wafer-Level Packaging of MEMS Devices

PROJECT TITLE :

Development of a 3-D Process Technology for Wafer-Level Packaging of MEMS Devices

ABSTRACT:

This paper presents a straightforward and low-price 3-D process technology for the wafer-level packaging (WLP) of microelectromechanical system (MEMS) devices. A tiny-sized WLP (1.zero$,times,$1.0$,times,$zero.thirty five mm) with a hermetically sealed cavity for the moving parts of MEMS devices was fabricated by using specially designed processes. The WLP was developed using 3 key techniques: through-wafer interconnection, wafer bonding, and bilateral face-MEMS fabrication. The expense and complexity of processes like silicon deep reactive ion etching and electroplating that arise from bilateral processing for through-wafer interconnection were overcome by using bulk micromachining technology. The fabricated WLP chips with a bonding area of 0.314 $rm mm^2$ showed a median shear strength of 9.seventy four $rm kg/rm mm^2$ and a leak rate less than 7$,times 10^-10~rm mbar.rm cc/rm sec$. Additionally, the chips had less than zero.one dB insertion loss before and once reliability testing. This newly developed 3-D method technology may be a good candidate for WLP MEMS fabrication as a result of it's simple and value-effective.

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