Analysis of the Electronic Assembly Repair Process for Lead-Free Parts Under Combined Loading Conditions PROJECT TITLE :Analysis of the Electronic Assembly Repair Process for Lead-Free Parts Under Combined Loading ConditionsABSTRACT: The conversion from tin–lead (SnPb) to lead-free electronics has created concern amongst engineers regarding the reliability of electronic assemblies and therefore the ramifications that reliability changes could have on the life-cycle cost and availability of essential systems that use lead-free electronics. In this paper, the impact of lead-free solder on the repair of electronic assemblies subject to combined thermal and vibration loading is studied. The cost, repair time, and availability of boards are quantified using a previously developed repair simulator for a check board developed and tested by the Joint Council on Aging Aircraft & Joint Council on Pollution Prevention that features ceramic leadless chip carrier, thin little define package, and plastic ball grid array packaged elements using SnPb and lead-free solders. This paper describes the method of calibrating a physics-of-failure reliability simulator using experimental highly accelerated life testing test results for a selected board assembly and using the calibrated model to get failure distributions corresponding to combined thermal and vibration loading over an actual product life cycle for use within the repair simulator. The results of the repair simulation indicate that longer dwell times appear to cause more harm than larger $Delta T$; below combined loading conditions, SnPb seems to be additional reliable than tin–silver–copper (for the board and components considered during this paper) and therefore, repair value is lower; and the quantity of failures and repair times track repair costs (relying on the capacity of repair process). Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Silicon Platform With Vertically Aligned Carbon Nanotubes for Enhancing Thermal Conduction in Hybrid Optoelectronic Integration Effect of Surface Roughness on Paper Substrate Circuit Board