Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI

PROJECT TITLE :

Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI

ABSTRACT:

Gaussian random numbers (GRNs) generated by central limit theorem (CLT) suffer from errors because of deviation from ideal Gaussian behavior for any finite variety of additions. In this paper, we tend to can show that it is potential to compensate the error in CLT, thereby correcting the resultant likelihood density perform, significantly within the tail regions. We tend to will offer a close mathematical analysis to quantify the error in CLT. This provides a style space with more than four degrees of freedom to create a selection of GRN generators (GRNGs). A framework utilizes this style area to come up with customized hardware architectures. We have a tendency to will demonstrate styles of 5 completely different architectures of GRNGs, that vary in terms of consumed memory, logic slices, and multipliers on field-programmable gate array. Similarly, depending upon application, these architectures exhibit statistical accuracy from low (4σ) to extremely high (12σ). A comparison with previously published styles clearly indicate benefits of this technique in terms of each consumed hardware resources and accuracy. We can additionally offer synthesis results of same designs in application-specific integrated circuit using 65-nm standard cell library. Finally, we tend to will highlight some shortcomings associated with such architectures followed by their remedies.

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