Sleep power minimisation using adaptive duty-cycling of DC–DC converters in state-retentive systems PROJECT TITLE :Sleep power minimisation using adaptive duty-cycling of DC–DC converters in state-retentive systemsABSTRACT:Aggressive power management techniques, which combine hardware and software solutions, are fundamental for embedded computing platforms today, especially if they are battery operated. This paper proposes an adaptive low-level algorithm, which modulates the DC-DC converter activation for minimising quiescent current consumption. This algorithm allows a discontinuous usage of the DC-DC converter during the sleep time, without requiring modification in the user's main program, by powering the system solely with the internal DC-DC converter capacitor and without using any other additional capacitors as an energy buffer. The algorithm computes the maximum interval between consecutive wake-ups necessary for the capacitor recharging at run-time. Intervals are decided by taking into account both the global leakage and the temperature-dependent variations of the capacitor. The proposed solution significantly enhances the lifetime of applications with a low activity rate, such as wireless sensor networks, while still guaranteeing efficient power delivery for high-current demand intervals. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductor Low-jitter, high-linearity current-controlled complementary metal oxide semiconductor relaxation oscillator with optimised floating capacitors
