PROJECT TITLE :

On the Area and Energy Scalability of Wireless Network-on-Chip: A Model-Based Benchmarked Design Space Exploration

ABSTRACT:

Networks-on-chip (NoCs) are rising because the way to interconnect the processing cores and the memory within a chip multiprocessor. As recent years have seen a vital increase in the quantity of cores per chip, it's crucial to guarantee the scalability of NoCs so as to avoid communication to become the following performance bottleneck in multicore processors. Among different alternatives, the concept of wireless network-on-chip (WNoC) has been proposed, wherein on-chip antennas would offer native broadcast capabilities resulting in enhanced network performance. Since energy consumption and chip space are the 2 primary constraints, this work is aimed to explore the realm and energy implications of scaling a WNoC in terms of: one) the amount of cores within the chip, and a couple of) the capability of every link in the network. To this end, an integral design area exploration is performed, covering implementation aspects (area and energy), communication aspects (link capacity), and network-level issues (number of cores and network architecture). The study is entirely based upon analytical models, that can enable to benchmark the WNoC scalability against a baseline NoC. Eventually, this investigation can give qualitative and quantitative guidelines for the look of future transceivers for wireless on-chip communication.