VLSI Architecture Design of FM0/Manchester Codec With 100% Hardware Utilization Rate for DSRC-Based Sensor Nodes in ITS Applications


Dedicated short-vary Communication (DSRC) plays an vital role in sensor networking for intelligent transportation system applications. How to achieve a better hardware potency becomes an engaging issue to design every vital building bock in sensor node. DSRC standards usually adopt either FM0 code or Manchester code as a coding technique to reinforce signal reliability. During this paper, a totally reused VLSI architecture of FM0/Manchester codec with a hardware utilization rate (HUR) of a hundred% is proposed for DSRC-primarily based sensor node. It's based mostly on the half-cycle processing model (HCPM). The HCPM includes three core techniques: one) half-cycle logic partition; two) reused-based mostly retiming; and three) Boolean function reshaping. The HCPM can improve the HUR of FM0/Manchester codec from twenty seven.thirty three% to 100percent with the reduction of the transistor count from 86 to sixty six. A a hundredpercent HUR suggests that every transistor is activated; thus, a more power is consumed. With a design tradeoff between HUR and power consumption, this paper still presents a higher energy efficiency. This paper is realized in TSMC zero.18-μm 1P6M CMOS technology. The silicon space of core circuit is thirty three × a hundred and twenty μm2. The experiment results demonstrate that this paper presents a competitive performance with a hundredpercent HUR compared with the present works. With this paper, DSRC-based mostly sensor nodes will gift a one hundredpercent HUR FM0/Manchester codec, fully supporting DSRC standards of Europe, USA, and Japan.

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