PROJECT TITLE :

Applying Model Checking to Industrial-Sized PLC Programs

ABSTRACT:

Programmable logic controllers (PLCs) are embedded computers widely utilized in industrial control systems. Ensuring that a PLC software complies with its specification is a challenging task. Formal verification has become a suggested follow to make sure the correctness of safety-vital software, however remains underused in business due to the complexity of building and managing formal models of real applications. In this paper, we propose a general methodology to perform automated model checking of complicated properties expressed in temporal logics [e.g., computation tree logic (CTL) and linear temporal logic (LTL)] on PLC programs. This methodology relies on an intermediate model (IM) meant to transform PLC programs written in numerous standard languages [structured text (ST), sequential perform chart (SFC), etc.] to different modeling languages of verification tools. We tend to present the syntax and semantics of the IM, and the transformation rules of the ST and SFC languages to the nuXmv model checker passing through the IM. Finally, two real cases studies of the European Organization for Nuclear Analysis (CERN) PLC programs, written mainly within the ST language, are presented to illustrate and validate the proposed approach.