PROJECT TITLE :

High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion

ABSTRACT:

Aiming at protection of high speed knowledge, field programmable gate array (FPGA)-primarily based advanced encryption standard (AES) design is proposed here. Deep investigation into the logical operations of AES regarding FPGA architectures ends up in 2 efficient pipelining structures for the AES hardware implementation. The two design choices permit users to form a trade-off among speed, resource usage and power consumption. Yet, a brand new key enlargement scheme is proposed to address the potential problems of existing key enlargement theme employed in AES. The proposed key growth scheme with further non-linear operations will increase the complexity of cracking keys by up to 2(N - 1) times for N-spherical AES. The proposed style is evaluated on numerous FPGA devices and is compared with several existing AES implementations. In terms of both throughput and throughput per slice, the proposed design will overcome most existing styles and achieves a throughput of 75.9 Gbps on a latest FPGA device. Two parallel implementations of the proposed style will meet the $64000-time encryption/decryption demand for one hundred Gbps knowledge rate. Furthermore, the proposed AES style is implemented on the Zynq xc7z020 FPGA platform, demonstrating its application to image encryption.