Author’s Reply to “Comments on ‘Optimization of a Compact I–V Model for Graphene FETs: Extending Parameter Scalability for Circuit Design Exploration’ ” S. Frégonèse a

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Author’s Reply to “Comments on 'Optimization of a Compact I–V Model for Graphene FETs: Extending Parameter Scalability for Circuit Design Exploration’ ” S. Frégonèse a

ABSTRACT:

We tend to appreciate the careful analysis and comments by Frégonèse and Zimmer [one] with respect to [2], where they show that the model proposed in [three] accurately reproduces experimental knowledge from graphene FETs (GFETs) when an acceptable smoothing issue is used. In [a pair of], we have proposed an extension of this model by Frégonèse et al. [3] with an exact calculation of a denominator. We tend to compared the model extension with the original work. Unfortunately, we have a tendency to did not use a appropriate smoothing factor in our comparison, which cause a robust artifact within the calculations and was absent in the exact solution. Following the argument in [one], we agree with our colleagues that there's no artifact at the Dirac purpose in their GFET compact-model when a proper smoothing issue is employed. We tend to were not conscious of the need of such a factor in specific cases when implementing the model as a result of it's not mentioned in [3]; thus, we tend to apologize for misrepresenting their work.

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