Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application


Behavior of adiabatic logic circuits in weak inversion or subthreshold regime is analyzed thorough for the first time within the literature to make nice improvement in ultralow-power circuit design. This novel approach is efficacious in low-speed operations where power consumption and longevity are the pivotal concerns rather than performance. The schematic and layout of a 4-bit carry look ahead adder (CLA) has been implemented to show the workability of the proposed logic. The result of temperature and method parameter variations on subthreshold adiabatic logic-primarily based 4-bit CLA has also been addressed separately. Postlayout simulations show that subthreshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. Results are validated through extensive simulations in twenty two-nm CMOS technology using CADENCE SPICE Spectra.

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