Prevention of Cracking From RDL Stress and Dicing Defects in Glass Substrates


Glass substrates have outstanding electrical properties, tailorable coefficient of thermal growth (CTE), high mechanical rigidity, availability in large and thin panel form, and sleek surface for fine line fabrication, and so, have gained increased attention and interest in microelectronics trade since 2010. While thin glass packaging offers such a plethora of benefits, glass may be a brittle material and thus is prone to failure when copper wiring and polymer layers are deposited on it. This experimental and theoretical work aims to understand the mechanics of glass cracking as a result of stress development from multilayer wiring, defect formation from panel dicing, and thermal cycling, then style a resolution to stop such cracks and demonstrate this solution. Dicing defects are simulated by adding a crack into the free fringe of the glass and therefore the energy accessible for crack propagation, G, is determined through a finite component based mostly fracture mechanics approach. Moisture is well known to lower surface energy, ensuing in a lower essential energy release rate for glass (GC) in the presence of moisture or water and, at the defect sizes measured, G reaches GC, indicating that the samples can crack whereas dicing in water. With thinner dielectric material, optimized dicing process, improved glass-polymer adhesion, and solder resist pullback, it's seen that glass cracking and glasspolymer delamination can be eliminated during dicing and subsequent thermal cycling.

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