3-D integration provides a pathway to achieve high performance microsystems through bonding and interconnection of best-of-breed materials and devices. Bonding of device layers can be accomplished by dielectric bonding and/or metal–metal interconnect bonding with a number of metal–metal systems currently under development. RTI has been investigating Cu–Cu and Cu/Sn–Cu interconnect processes for high density area array applications. The interconnect pad fabrication processes and the interconnect bonding conditions (pressure and temperature) required for the formation of low resistance (10's of ${rm m}Omega$), high yielding (${geq}{99.98}%$ bond yield), and reliable interconnects are described. The effects of thermal reliability testing (aging) on electrical connectivity and mechanical strength are presented. Results from the two metal–metal interconnect bonding systems are compared in terms of ease of assembly and small pitch (sub-15 $mu{rm m}$) scaling. Methods for obtaining high bond yield at smaller pitches are discussed.

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