Modeling Static Delay Variations in Push–Pull CMOS Digital Logic Circuits Due to Electrical Disturbances in the Power Supply


Soft errors will occur in digital integrated circuits (ICs) as a results of an electromagnetic disturbance, like might result from an electrical fast transient (EFT). Several soft errors come back from changes in propagation delays through digital logic, which are caused by changes within the on-die power provide voltage. An analytical model was developed to predict timing variations in digital logic as a results of variations in the ability provide voltage. The derivation of the analytical delay model is reported. The model was validated experimentally by applying EFTs to a hoop oscillator built during a take a look at IC. The predicted and measured ring oscillator frequencies (or periods) agreed within a relative error of less than 2.0%. To further validate the approach, the model was applied to test the response of more complicated circuits consisting of NAND/NOR logic gates, binary adders, dynamic logic gates, and transmission gates. The circuits were fabricated on a zero.five μm test IC and simulated on two further process technologies (0.18 μm and forty five nm). The model performed well in each case with a maximum relative error of five.sixp.c, verifying the applicability of the model for analyzing complex logic circuits within a selection of method technologies. The proposed delay model will be employed by IC style engineers to predict and perceive the modification within the propagation delay through logic circuits because of the disturbed power supply.

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