PROJECT TITLE :
Placement Density Aware Power Switch Planning Methodology for Power Gating Designs
As advances in manufacture technology, leakage current will increase dramatically in fashionable ICs. By turning off supply voltage during a low-power domain with power switches, power gating becomes a helpful technique in resolving this downside. Since number and locations of power switches have nice impact on chip area and IR-drop, an economical and effective approach to insert power switches is required for the power gating designs. Unlike previous works using the greedy algorithm to handle this downside, this paper uses a simplified model to approximate required equivalent resistance of power switches in a very low-power domain, and then determines number and types of power switches primarily based on the value. In order to cut back impact on preplaced commonplace cells, we have a tendency to additionally propose a mathematical approach to find locations with less placement density to position power switches. The proposed methodology was integrated into a real-design flow. Experimental results demonstrate that our approach will insert less number of power switches and still satisfy the IR-drop constraint than different approaches.
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