PROJECT TITLE :

A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection

ABSTRACT:

On-chip security is an emerging challenge in the design of embedded systems with intellectual property (IP) cores. Traditionally this challenge is addressed using unexpected style techniques with separate style objectives of secure style for testability (DfT), and IP core protection. However, in this paper, we will argue that such style approaches can incur high prices. Underpinning this argument, we tend to propose a unique style methodology, known as Secure Take a look at and IP core Protection (STEP), that aims to deal with the joint objective of IP core protection and secure testing. To make sure that this objective is achieved at an occasional cost, the STEP style methodology employs common key integrated hardware. This hardware is incorporated in the system through an automated design conversion technique, that will be easily merged into the electronic style automation (EDA) tool chain. We have a tendency to evaluate the effectiveness of our proposed design methodology considering varied implementations of advanced encryption normal (AES) systems as case studies. We tend to show that our proposed style methodology benefits from style automation with high security, and protection at the value of low area, and power consumption overheads, compared with ancient design methodologies.