PROJECT TITLE :

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion

ABSTRACT:

A 3.5 GHz digital fractional-N PLL in sixty five nm CMOS technology is presented that achieves section noise and spurious tone performance cherish those of a high-performance analog PLL. It is enabled by a brand new second-order frequency-to-digital converter that uses a dual-mode ring oscillator and digital logic instead of a charge pump and ADC. It conjointly incorporates a new technique to scale back excess part noise that might preferably be caused by component mismatches when the DCO input is close to integer boundaries. The PLL's largest in-band fractional spur is -60 dBc, its worst-case reference spur is -81 dBc, and its part noise is -ninety three, -126, and -151 dBc/Hz at offsets of a hundred kHz, 1 MHz, and twenty MHz, respectively. Its active area is zero.34 mm a pair of and it dissipates fifteen.six mW from a one V supply.