PROJECT TITLE :

A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links

ABSTRACT:

A speedy-on/off transceiver for embedded clock design that enables energy proportional Communication over the serial link is presented. In an energy proportional link, energy consumed by serial link is proportional to the number of knowledge communicated. Energy proportionality will be achieved by scaling the serial link power linearly with the link utilization, and fine grained fast power state transition (rapid-on/off) is one such technique that will achieve this objective. In this paper, architecture and circuit techniques to attain rapid-on/off in PLL, transmitter and receiver are discussed. Background section calibration technique in PLL and CDR part calibration logic in receiver enable instantaneous lock on power-on. The proposed transceiver demonstrates power scalability with a wide selection of link utilization and, thus, helps in improving overall system potency. Fabricated in 65 nm CMOS technology, the seven Gb/s transceiver achieves power-on-lock in less than twenty ns. Proposed PLL achieves power-on-lock in one ns. The transceiver achieves power scaling by forty four $times$ (sixty three.seven mW-to-1.forty three mW) and energy efficiency degradation by solely 2.a pair of$times$ (9.one pJ/bit-to-20.five pJ/bit), when the effective data rate (link utilization) changes by one hundred$times$ (7 Gb/s-to-70 Mb/s). The proposed transceiver occupies a full of life die area of 0.39 mm$^2$.