Dynamic Architecture and Frequency Scaling in 0.8–1.2 GS/s 7 b Subranging ADC


Dynamic Architecture and Frequency Scaling (DAFS) is shown to understand superlinear power scaling in high-speed analog-to-digital converters (ADCs). To realize both high-speed operation and low power consumption, the ADC design is reconfigured between binary search and flash every clock cycle, counting on the conversion delay. The proposed binary search/flash architecture reconfigurable ADC will be implemented with solely a small modification to standard binary search ADCs. By live configuring, the flash operation is adaptively performed when an excess delay is detected. DAFS not only considerably improves the ability scaling however additionally compensates for transistor speed shifts because of method, voltage and temperature (PVT) variations. Therefore, DAFS can be used to improve the look margin of high-speed ADCs. A prototype subranging ADC fabricated in sixty five nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of thirty six.a pair of dB with a Nyquist input frequency. DAFS is active between 820–1220 MS/s and achieves peak power reduction of 30p.c, when compared with the ability scaling when DAFS is disabled. A peak FoM of eighty five fJ/conv. was obtained at 820 MS/s, which is almost a twofold improvement over that of previously reported subranging ADCs.

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