Look-up table-based digital predistorter implementation for field programmable gate arrays using long-term evolution signals with 60 mhz bandwidth


This study discusses the implementation of a digital predistorter to linearise radiofrequency (RF) power amplifiers, using input signals 60 MHz in bandwidth. The digital predistorter characterisation procedure is performed on a digital signal processor, using a memory polynomial modelling technique with QR-based recursive least squares (QR-RLS) as the extraction procedure. A multiple look-up table design for the memory polynomial predistorter is introduced, and by using fixed-point operations, reduces the processing latency considerably when compared with a floating-point-based predistorter implementation on a field programmable gate array (FPGA). Linearisation results are shown for a laterally diffused metal oxide semi-conductor (LDMOS)-based power amplifier (PA) biased in class AB operation with a three-carrier long-term evolution-time division duplex (LTE-TDD) input signal. Combining both the optimised predistortion coefficient extraction and predistorter implementation gives up to 20 dBc improvement in the adjacent channel and meets the wireless Communication standard requirements.

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