PROJECT TITLE :
Full-Wafer Voltage Contrast Inspection for Detection of BEOL Defects
This paper details an application where E-beam inspection (EBI) can be used for one hundred% full wafer inspection, typically considered a legendary target for EBI. For method layers where the line-widths and defects of interest are large, terribly large pixel size and high scan frequency will be used, thereby making full wafer inspection feasible. The metal layers in the back-end-of-line work this bill when scanned in voltage contrast (VC) mode. Shorts or opens at any previous layer connected to the surface nodes will cause a VC signal, therefore the electrical health of every wafer is assessed for multiple layers simultaneously across the total wafer. The advantage of this scan is that failure sites can be identified and somewhat localized well before wafer final take a look at. This application is additional appropriate for semi-mature technologies where there are few defects per wafer, and therefore a full wafer scan is needed to catch a cheap range of defects. The challenge with this type inspection is in identification of the foundation cause. A range of studies to map VC defect strength to varieties of physical defects are described. These studies demonstrated that this system successfully finds yield limiting defects, but not all yield limiting defects can be detected. A plan for the way to use the VC inspection to search out root cause is presented.
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