3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature


Excellent electrostatic management offered by gate-all-around (GAA) geometry makes multinanowire (multi-NW) MOSFET a promising candidate for sub-ten-nm technology nodes. Unfortunately, the GAA geometry is inclined to the increased self-heating due to poor heat dissipation from the nanowires (NWs) to the substrate. Therefore, an understanding of spatio-temporal temperature rise, AT(x, y, z; t), at the NW level is vital for predicting activity-induced variability within an IC, and characterization of numerous reliability issues, like, NBTI, PBTI, HCI, and TDDB that rely sensitively on self-heating. During this paper, a three-D electrothermal simulation model is developed to explore and interpret self-heating and warmth dissipation in GAA devices. Our results determine complicated heat dissipation pathways characterized by multiple time constants. 1st, the nanowires heat up quickly (τGAA-NW ~ nSec), then heat spreads the gate contact pad (τG-pad ~ 100 nSec), and at last, the warmth exits through the warmth sink at the underside of the substrate (τsub ~ mSec). A systematic thermoreflectance measurement of temperature helps us to identify the time constants, and validates the model. Our results have implications for the design, characterization, circuit-operation, and reliability of high-performance GAA devices.

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