Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints


In three-D integrated circuits, through silicon via (TSV) could be a crucial enabling technique to provide vertical connections. But, it might suffer from several reliability problems like undercut, misalignment, or random open defects. Varied fault-tolerance mechanisms are proposed in literature to improve yield, at the value of important area overhead. During this paper, we have a tendency to specialize in the structure that uses one spare TSV for a group of original TSVs, and study the optimal assignment of spare TSVs beneath yield and timing constraints to attenuate the overall area overhead. We tend to show that such drawback can be modeled as a constrained graph decomposition drawback. 2 efficient heuristics are additional developed to deal with this problem. Experimental results show that underneath the same yield and timing constraints, our heuristic can reduce the area overhead induced by the fault-tolerance mechanisms by up to sixty one%, compared with a seemingly a lot of intuitive nearest-neighbor-primarily based heuristic.

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