PROJECT TITLE :
On the Energy-Efficiency of Byte-Addressable Non-Volatile Memory
Non-volatile memory (NVM) technology holds promise to switch SRAM and DRAM at varied levels of the memory hierarchy. The interest in NVM is motivated by the issue faced in scaling DRAM beyond 22 nm and, long-term, lower value per bit. While giving higher density and negligible static power (leakage and refresh), NVM suffers increased latency and energy per memory access. This paper develops energy and performance models of memory systems and applies them to understand the energy-efficiency of replacing or complementing DRAM with NVM. Our analysis focusses on the applying of NVM in main memory. We tend to demonstrate that NVM such as STT-RAM and RRAM is energy-efficient for memory sizes commonly utilized in servers and high-finish workstations, but PCM isn't. Furthermore, the model is compatible to quickly evaluate the impact of changes to the model parameters, that may be achieved through optimization of the memory architecture, and to work out the key parameters that impact system-level energy and performance.
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