A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems PROJECT TITLE :A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core SystemsABSTRACT:Network-on-Chip (NoC) paradigm is rapidly evolving into an economical interconnection network to handle the strict Communication needs between the increasing variety of cores on one chip. Diminishing transistor size is creating the NoC increasingly liable to both hard faults and soft errors. This paper concentrates on soft errors in NoCs. A soft error in an NoC router leads to important consequences like information corruption, packet retransmission and deadlock among others. To the current finish, we tend to propose Soft Error Tolerant NoC Router (STNR) design, that's capable of detecting and recovering from soft errors occurring in different control stages of the routing pipeline. STNR exploits the utilization of idle cycles inherent in NoC packet routing pipeline to perform time redundant executions necessary for soft error tolerance. In doing so, STNR is in a position to detect and correct all single transient faults within the control stages of the pipeline. Simulation results using PARSEC and SPLASH-two benchmarks show that STNR is able to accomplish such high level of sentimental error protection with a minimal impact on latency (a rise of one.7 and 1.half dozen percent respectively). Additionally, STNR incurs an space overhead of seven % and power overhead of 13 p.c as compared to the baseline unprotected router. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Analysis of Torques in Single-Side Linear Induction Motor With Transverse Asymmetry for Linear Metro Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures
