Unexpected Latch-Up Through CMOS Triple-Well Structures PROJECT TITLE :Unexpected Latch-Up Through CMOS Triple-Well StructuresABSTRACT:Unexpected device interactions between ESD diodes and NMOS clamps in isolated P-well (triple well) are observed. This could lead to an SCR-like I-V behavior in TLP measurements and poses a latch-up risk. The reason behind this interaction is being analyzed using equivalent circuits with parasitic devices and by TCAD simulations. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest A Delay-Rational Model of Lossy Multiconductor Transmission Lines With Frequency-Independent Per-Unit-Length Parameters Low-Complexity Bayesian Estimation of Cluster-Sparse Channels