PROJECT TITLE :
Unexpected Latch-Up Through CMOS Triple-Well Structures
Unexpected device interactions between ESD diodes and NMOS clamps in isolated P-well (triple well) are observed. This could lead to an SCR-like I-V behavior in TLP measurements and poses a latch-up risk. The reason behind this interaction is being analyzed using equivalent circuits with parasitic devices and by TCAD simulations.
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