Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors

PROJECT TITLE :

Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors

ABSTRACT:

Reliability should be identified as the most vital challenge in future nano-scale very large scale integration (VLSI) implementation technologies for the event of complex integrated systems. Normally, fault tolerance (FT) in a conventional system is achieved by increasing its redundancy, that also implies higher implementation costs and lower performance that typically makes it even infeasible. In distinction to custom approaches, a new class of applications is categorized during this paper, which is inherently capable of absorbing some degrees of vulnerability and providing FT primarily based on their natural properties. Neural networks are good indicators of imprecision-tolerant applications. We tend to have additionally proposed a replacement class of FT techniques known as relaxed fault-tolerant (RFT) techniques that are developed for VLSI implementation of imprecision-tolerant applications. The most advantage of RFT techniques with respect to traditional FT solutions is that they exploit inherent FT of different applications to reduce their implementation prices whereas improving their performance. To show the applicability furthermore because the efficiency of the RFT technique, the experimental results for implementation of a face-recognition computationally intensive neural network and its corresponding RFT realization are presented during this paper. The results demonstrate promising higher performance of artificial neural network VLSI solutions for complex applications in faulty nano-scale implementation environments.

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