Failure Analysis of 1200-V/150-A SiC MOSFET Under Repetitive Pulsed Overcurrent Conditions

PROJECT TITLE :

Failure Analysis of 1200-V/150-A SiC MOSFET Under Repetitive Pulsed Overcurrent Conditions

ABSTRACT:

SiC MOSFETs are a leading option for increasing the ability density of Power Electronics; but, for these devices to supersede the Si insulated-gate bipolar transistor, their characteristics must be any understood. 2 SiC vertically oriented planar gate D-MOSFETs rated for 1200 V/one hundred fifty A were repetitively subjected to pulsed overcurrent conditions to evaluate their failure mode due to the current common supply of electrical stress. This analysis supplements recent work that demonstrated the long term reliability of these same devices [one]. Using an RLC pulse-ring-down test bed, these devices laborious-switched 60zero A peak current pulses, such as a current density of 1500 A/cm2. Throughout testing, static characteristics of the devices like $B_rm VDSS$ , $R_rm DS(rm on)$, and $V_rm GS(rm th)$ were measured with a high power device analyzer. The experimental results indicated that a conductive path was shaped through the gate oxide; TCAD simulations revealed localized heating at the SiC/SiO2 interface as a result of the intense high current density gift within the device's JFET region. However, the high peak currents and repetition rates required to provide the conductive path through the gate oxide demonstrate the robustness of SiC MOSFETs underneath the pulsed overcurrent conditions common in Power Electronic applications.

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