PROJECT TITLE :
Parallel Sparse Matrix Solution for Circuit Simulation on FPGAs
SPICE is that the de facto commonplace for circuit simulation. However, correct SPICE simulations of nowadays’s sub-micron circuits can usually take days or even weeks on conventional processors. A SPICE simulation is an iterative method that consists of two phases per iteration: model analysis followed by a matrix answer. The model analysis section has been found to be simply parallelizable, unlike the next phase, that involves the answer of highly sparse and asymmetric matrices. In this paper, we tend to present an FPGA implementation of a sparse matrix solver, geared towards matrices that arise in SPICE circuit simulations. Our approach combines static pivoting with symbolic analysis to compute an accurate task flow-graph which efficiently exploits parallelism at multiple granularities and sustains high floating-purpose knowledge rates. We tend to also present a quantitative comparison between the performance of our hardware prototype and state-of-the-art software packages running on a general-purpose PC. We report average speed-ups of 9.sixty five$times$ , eleven.eighty three $times$, and 17.21 $times$ against UMFPACK, KLU, and Kundert Sparse matrix packages, respectively.
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