Domain Wall Memory-Layout, Circuit and Synergistic Systems


Domain wall memory (DWM) is gaining vital attention for embedded cache application thanks to low standby power, wonderful retention, and skill to store multiple bits per cell. Additionally, it provides quick access time, good endurance, and good retention. However, it suffers from poor write latency, shift latency, shift power, and write power. DWM is sequential in nature and latency of scan/write operations depends on the offset of the bit from the scan/write head. This paper investigates the circuit style challenges such as bitcell layout, head positioning, utilization factor of the nanowire, shift power, shift latency, and provides solutions to deal with these issues. A synergistic system is proposed by combining circuit techniques like merged read/write heads (for compact layout), flipped-bitcell and shift gating (for shift power optimization), wordline strapping (for access latency), shift circuit design with two micro-architectural techniques: one) segmented cache and a couple of) workload-aware dynamic shift and write current boosting to appreciate energy-economical and strong DWM cache. Simulations show 3–33% performance and one.a pair of–14.4X power consumption improvement for cache segregation and a pair of.five–thirty one% performance and 1.3–fourteen.9X power enhancement for dynamic current boosting over a wide selection of PARSEC benchmarks.

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