PROJECT TITLE :
Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS
As technology nodes approach deca-nanometer dimensions, many phenomena threaten the binary correctness of processor operation. Pc architects usually enhance their styles with reliability, availability and serviceability (RAS) schemes to correct such errors, in many cases at the cost of extra clock cycles, that, in flip, leads to processor performance variability. The goal of the current paper is to soak up this variability using Dynamic Voltage and Frequency Scaling (DVFS). A closed-loop implementation is proposed, which configures the clock frequency based on observed metrics that encapsulate performance variability due to RAS mechanisms. That approach, performance dependability and predictability is achieved. We simulate the transient and steady state behavior of our approach, reporting responsiveness inside but one ms. We also assess our plan using the facility model of real processor and report a maximum energy overhead of roughly 10 p.c for dependable performance in the presence of RAS temporal overheads.
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