PROJECT TITLE :
A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling
This paper presents never-ending-rate reference-less clock and data recovery (CDR) circuit that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking techniques to scale back style complexity for the [*fr1]-rate knowledge recovery. Within the proposed receiver, the use of wideband injection-locked oscillator (ILO) greatly suppresses its phase noise while the narrowband digital part tracking loop (DPTL) tunes retiming part. For wide-vary and continuous-rate operation, four circuit techniques have been adopted: a VCO with active inductance load for low VCO gain at high frequency, a good-vary digitally-controlled delay line (DCDL) with adaptive band selection, a linearized delay control unit with CM-to-delay conversion technique, and a rough frequency detection scheme to drive the free-running oscillator frequency toward injection locking. The prototype CDR, fabricated in low power CMOS 65 nm technology, successfully detects 0.eight–half dozen.5 Gb/s data rates over five FR4 trace with PRBS pattern satisfying . The ability efficiency was a pair of.four mW/Gb/s at vi.five Gb/s.
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