PROJECT TITLE :

Register – Less NULL Conventional Logic - 2017

ABSTRACT:

NULL Convention Logic (NCL) may be a promising style paradigm for constructing low-power strong asynchronous circuits. The conventional NCL paradigm requires pipeline registers for separating two neighboring logic blocks, and people registers will account for up to thirty fivepercent of the overall power consumption of the NCL circuit. This transient presents the Register-Less NCL (RL-NCL) style paradigm, which achieves low power consumption by eliminating pipeline registers, simplifying the control circuit, and supporting fine-grained power gating to mitigate the leakage power of sleeping logic blocks. Compared with the traditional NCL counterpart, the RL-NCL implementation of an eight-bit 5-stage pipelined Kogge-Stone adder will cut back power dissipation by 56.4%-72.5percent for the input data rate starting from 10 to 900 MHz. Moreover, the RL-NCL implementation will cut back the transistor count of the adder by forty nine.fivep.c.