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  4. A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis - 2016
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Category: MTech VLSI Projects
By MTech Projects
MTech Projects
01.Jun
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A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis - 2016

PROJECT TITLE :

A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis - 2016

ABSTRACT:

Procedures that were described earlier increase the accuracy of defect diagnosis by ignoring little subsets of tests in order to supply smaller candidate fault sets. The premise behind these procedures is that almost all of the tests during a given take a look at set are useful for defect diagnosis, and solely little numbers of tests need to be ignored. This paper makes the new observation that it is doable to use tiny subsets of tests to get more accurate diagnosis results. This paper describes a procedure that starts from an empty test set, and adds tests one by one. The take a look at selected at every iteration is that the one that leads to the tiniest candidate fault set. The addition of tests increases the number of candidate faults gradually. Experimental results for benchmark circuits demonstrate that the addition of tests provides a lot of candidate fault sets with higher degrees of accuracy than the removal of tests. One of these candidate fault sets can be used for failure analysis.

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  • Design and simulation of single layered Logic Generator Block using Quantum Dot Cellular Automata - 2016
  • A Method of One-Pass Seed Generation for LFSR-Based Deterministic/Pseudo-Random Testing of Static Faults - 2015
  • ( 4+2 log n ) Delta-G Modulo-(2^ Parallel Prefix n-3) Adder via Double Representation of Residues in [0,2] - 2015
  • Low-power Implementation of Mitchell's Approximate Logarithmic Multiplication for Convolutional Neural Networks - 2018
  • Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis - 2018
  • NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices - 2016
  • Hardware efficient multiplier-less multi-level 2D DWT architecture without off-chip RAM - 2017
  • A Novel Quantum-Dot Cellular Automata X-bit x 32-bit SRAM - 2016
  • Code Compression for Embedded Systems Using Separated Dictionaries - 2017
  • Design and Analysis of Multiplier Using Approximate 15-4 Compressor - 2017
  • ROOT
Previous article: Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories - 2016 Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories - 2016 Next article: Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST - 2016 Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST - 2016
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