PROJECT TITLE :

A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes - 2017

ABSTRACT:

This paper presents the look and implementation of memory-primarily based fast Fourier rework (FFT) processors with generalized economical, conflict-free address schemes. We tend to unified the conflict-free address schemes of three totally different FFT lengths, together with the one-power points, the common nonsingle-power points, and also the nonsingle-power points applied with a prime factor algorithm. Though the three cases differ in terms of decomposition, they are all compatible with memory-primarily based design by the means of the proposed address schemes. Moreover, the decomposition algorithm utilizes a method, named high-radix-small-butterfly (HRSB), to decrease the computation cycles and eliminate the complexity of the processing engine. Similarly, an efficient index generator, a simplified multipath delay commutator engine, and a unified Winograd Fourier transform algorithm butterfly core were also designed. We designed two FFT examples in long-term evolution system to verify the supply of the address scheme, together with a 2n (128-2048)-point FFT unit and a 35 totally different purpose (12-1296) DFT unit. Compared with previous works with similar address schemes, this paper supports additional generalized lengths and achieves a lot of versatile throughput.