Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping - 2017


This paper deals with the hardware implementation of the recently introduced Probabilistic Gradient-Descent Bit-Flipping (PGDBF) decoder. The PGDBF could be a new kind of hard-decision decoder for Low-Density Parity-Check (LDPC) code, with improved error correction performance due to the introduction of deliberate random perturbation within the computing units. Within the PGDBF, the random perturbation operates during the bit-flipping step, with the target to avoid the attraction of therefore-known as trapping-sets of the LDPC code. In this paper, we tend to propose an economical hardware design which minimizes the resource overhead required to implement the random perturbations of the PGDBF. Our architecture is predicated on the utilization of a short Random Sequence (SRS) that's duplicated to totally apply the PGDBF decoding rules, and on an optimization of the utmost finder unit. The generation of fine SRS is crucial to take care of the outstanding decoding performance of PGDBF, and we propose 2 different ways with equivalent hardware overheads, but with totally different behaviors on totally different LDPC codes. Our designs show that the improved PGDBF performance gains can be obtained with a terribly little further complexity, therefore providing a competitive laborious-call LDPC decoding answer for current standards.

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