PROJECT TITLE :
An Efficient O(N) Comparison-Free Sorting Algorithm - 2017
In this paper, we propose a unique sorting algorithm that kinds input information integer components on-the-fly while not any comparison operations between the information-comparison-free sorting. We tend to present a whole hardware structure, associated timing diagrams, and a proper mathematical proof, that show an overall sorting time, in terms of clock cycles, that's linearly proportional to the quantity of inputs, giving a speed complexity on the order of O(N). Our hardware-primarily based sorting algorithm precludes the need for SRAM-based memory or advanced circuitry, like pipelining structures, but rather uses straightforward registers to carry the binary elements and the elements' associated variety of occurrences within the input set, and uses matrix-mapping operations to perform the sorting process. Therefore, the total transistor count complexity is on the order of O(N). We evaluate an application-specified integrated circuit design of our sorting algorithm for a sample sorting of N = 1024 parts of size K = ten-bit using ninety-nm Taiwan Semiconductor Manufacturing Company (TSMC) technology with a one V power supply. Results verify that our sorting requires approximately 4-vi µs to kind the 1024 elements with a clock cycle time of 0.5 GHz, consumes 1.six mW of power, and incorporates a total transistor count of but 750 00zero.
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