Efficient Designs of Multi ported Memory on FPGA - 2017


The utilization of block RAMs (BRAMs) may be a critical performance factor for multiported memory designs on field-programmable gate arrays (FPGAs). Not solely will the excessive demand on BRAMs block the usage of BRAMs from alternative parts of a design, however the complicated routing between BRAMs and logic conjointly limits the operating frequency. This paper first introduces a whole new perspective and a more economical manner of using a conventional 2 reads one write (2R1W) memory as a 2R1W/4R memory. By exploiting the 2R1W/4R as the building block, this paper introduces a hierarchical design of 4R1W memory that requires twenty fivep.c fewer BRAMs than the previous approach of duplicating the 2R1W module. Memories with more browse/write ports will be extended from the proposed 2R1W/4R memory and the hierarchical 4R1W memory. Compared with previous xor-based mostly and live worth table-primarily based approaches, the proposed designs will, respectively, reduce up to fifty threep.c and 69% of BRAM usage for 4R2W memory designs with 8K-depth. For advanced multiported styles, the proposed BRAM-economical approaches will achieve higher clock frequencies by alleviating the complicated routing in an FPGA. For 4R3W memory with 8K-depth, the proposed style can save fifty threepercent of BRAMs and enhance the operating frequency by 20p.c.

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