Energy-Efficient Approximate Multiplier Design usingBit Significance-Driven Logic Compression - 2017

PROJECT TITLE :

Energy-Efficient Approximate Multiplier Design usingBit Significance-Driven Logic Compression - 2017

ABSTRACT:

Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can supply substantial reductions in circuit complexity, delay and energy consumption by relaxing accuracy necessities. During this paper, we propose a novel energy-efficient approximate multiplier style employing a significance-driven logic compression (SDLC) approach. Elementary to the current approach is an algorithmic and configurable lossy compression of the partial product rows based mostly on their progressive bit significance. This can be followed by the commutative remapping of the ensuing product terms to reduce the amount of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of vital paths is drastically reduced. A range of multipliers with completely different bit-widths (four-bit to 128-bit) are designed in SystemVerilog and synthesized using Synopsys Style Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in important delay and almost forty fivep.c in silicon space will be achieved for a 128-bit multiplier compared to an accurate equivalent. These gains are achieved with low accuracy losses estimated at but zero.00071 mean relative error. Additionally, we tend to demonstrate the energy-accuracy trade-offs for different degrees of compression, achieved through configurable logic clustering. In evaluating the effectiveness of our approach, a case study Image Processing application showed up to sixty eight.3% energy reduction with negligible losses in image quality expressed as peak signal-to-noise ratio (PSNR).

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