DSP48E Efficient Floating Point Multiplier Architectures on FPGA - 2017


This paper presents FPGA primarily based hardware architectures for floating point (FP) multipliers. The proposed multiplier architectures are aimed for single precision (SP), double precision (DP), double-extended precision (DEP) and quadruple precision (QP) implementation. This paper follows the quality computational flow for FP multiplication. The mantissa multiplications, the foremost advanced unit of the FP multiplication, are designed using efficient use of Karatsuba methodology integrated with the optimized used of in-built 25x18 DSP48E blocks obtainable on the Xilinx Virtex-5 onward FPGA devices. It conjointly combined with the other techniques (radix-four booth encoding for small multipliers, partial product reduction using 4:2, 3:two, 2:a pair of counters; compression of multioperands adders) used at places, to boost the planning. The proposed architectures out-performs the available state-of-theart, and used solely one-DSP48, 3 DSP-48, 6 DSP48 and eighteen DSP48 for SP, DP, DEP, and QP multipliers respectively.

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