One-Cycle Correction of Timing Errors in PipelinesWith Standard Clocked Elements - 2016 PROJECT TITLE : One-Cycle Correction of Timing Errors in PipelinesWith Standard Clocked Elements - 2016 ABSTRACT: One of the foremost aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires quick correction of timing errors. The fastest existing error correction technique imposes a 1-cycle time penalty solely, however it's restricted to two-phase transparent latch-primarily based pipelines. We perform one-cycle error correction by gating only the most latch in every stage of the pipeline that precedes a failed stage. This new methodology is applicable to widely used clocking components, like flip-flops and pulsed latches. As a result of it prevents inputs arriving at a stage, which is stalled, it will additionally be utilized in pipelines with multiple fan-in, fan-out, and looping. Simulations show an energy saving of eightpercent-twelvepercent with a target throughput of zero.nine directions per cycle, and 15%-eighteenp.c when the target is 0.eight. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Flip-Flops Timing Speculation Dynamic Voltage Scaling Timing Errors One-Cycle Time Penalty Two-Phase Transparent Latch-Based Pipelines One-Cycle Error Correction Main Latch Pulsed Latches Design Methodology for Voltage-Scaled Clock Distribution Networks - 2016 A Single-Ended With Dynamic Feedback Control 8T Sub threshold SRAM Cell - 2016
