PROJECT TITLE :
A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies - 2016
Performance degradation tolerance (PDT) has been shown to be able to effectively improve the yield, reliability, and lifelong of an electronic product. The focus of PDT is on the actual performance degrading faults (pdef) that only incur some performance degradation of a system while not inducing any computation errors. The basic idea is that as long as the defective chips containing only the pdef can provide acceptable performance for a few applications, they'll still be marketable. Important issues of PDT to be addressed embrace the portion of the pdef in an exceedingly faulty chip and their induced performance degradation. For a typical cache style, most of the attainable faults don't seem to be pdef. In this transient, we tend to propose a cache redesign method, referred to as PDT cache, where all practical faults in the info-storage cells of a cache (major half of the cache) will be transformed into pdef. By reworking this large variety of faults into pdef, a faulty cache becomes much additional doubtless to be still marketable. The proposed design exploits the prevailing hardware resources and the inherent error resilience scheme to cut back the incurred hardware overhead. The logic synthesis results show that the incurred hardware overhead is only half dozen.twenty ninep.c for a 32-kB cache. We tend to conjointly evaluate the induced performance degradation underneath numerous fault densities using the CPU200zero and CPU2006 benchmark programs. The results show that for a 32-kB cache style, when the fault density is <;onepercent, only zero.thirty onep.c performance degradation is incurred. In addition, the scalability of the PDT cache is also evaluated. The results show that a smaller hardware overhead is required for a larger cache, and also the performance degradation is freelance of the cache associativity and will even be smaller for a bigger cache beneath a given fault density.
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