Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications - 2015 PROJECT TITLE: Fully Reused VLSI Architecture of FM0Manchester Encoding Using SOLS Technique for DSRC Applications - 2015 ABSTRACT: The dedicated short-range Communication (DSRC) is an emerging technique to push the intelligent transportation system into our standard of living. The DSRC standards typically adopt FM0 and Manchester codes to achieve dc-balance, enhancing the signal reliability. Nevertheless, the coding-diversity between the FM0 and Manchester codes seriously limits the potential to style a totally reused VLSI design for each. In this project, the similarity-oriented logic simplification (SOLS) technique is proposed to overcome this limitation. The SOLS technique improves the hardware utilization rate from fifty seven.14% to a hundredp.c for both FM0 and Manchester encodings. The performance of this project is evaluated on the postlayout simulation in Taiwan Semiconductor Manufacturing Company (TSMC) zero.eighteen-µm 1P6M CMOS technology. The maximum operation frequency is 2 GHz and 90zero MHz for Manchester and FM0 encodings, respectively. The power consumption is one.fifty eight mW at a pair of GHz for Manchester encoding and 1.fourteen mW at 900 MHz for FM0 encoding. The core circuit space is 65.ninety eight × 30.forty three µm2. The encoding capability of this project will totally support the DSRC standards of America, Europe, and Japan. This project not only develops a fully reused VLSI architecture, but also exhibits an efficient performance compared with the existing works. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL - 2015 FPGA implementation of an advanced encoding and decoding architecture of polar codes - 2015
